Samsung, TSMC and Intel join ASML to build new technology barrier against China

Non-Chinese chipmakers rally around ASML to push High-NA EUV

New lithography standard puts them roughly 20 years ahead of China

Samsung aims to be first to apply High-NA EUV to sub-10nm DRAM

Samsung Electronics Vice Chairman Lee Jae-yong (second from left) poses for a photo with ASML CEO Peter Wennink and CTO Martin van den Brink after inspecting semiconductor equipment at ASML's headquarters in Eindhoven, the Netherlands, on June 14, 2022 (local time). [Samsung Electronics]

Over the past three weeks, this column has taken a close look at China's memory chipmakers — CXMT and YMTC. This week, the focus shifts to the other side: the non-Chinese semiconductor front forming in response to China's technological push.

Last week, Dutch lithography giant ASML and three of the world's leading chipmakers — Intel of the United States, Taiwan's TSMC and South Korea's Samsung Electronics — issued a series of joint announcements pledging to adopt High-NA EUV, the next generation of lithography equipment. The move signals that ASML, the world's sole producer of EUV lithography systems, is now working with Intel, TSMC and Samsung Electronics to jointly shape the standards and manufacturing infrastructure for next-generation semiconductor production.

Samsung Electronics said it plans to be the first in the industry to apply High-NA EUV to advanced DRAM mass production by 2028. TSMC disclosed plans to use High-NA in advanced process mass production from 2030. Intel is already ahead of both, having begun mass-producing chips using High-NA EUV.

The collaboration goes well beyond simply purchasing ASML equipment. ASML, Intel, TSMC and Samsung Electronics have agreed to jointly develop photomasks for High-NA EUV adoption. A photomask functions as a kind of circuit stencil, used to etch microscopic circuit patterns onto wafers. The partnership means the companies intend to build not just the tools but the surrounding manufacturing infrastructure and standards together.

The timing of these announcements is telling.

Just about a month ago, news that China had begun mass-producing its own domestically developed immersion DUV (deep ultraviolet) lithography equipment sent ripples through the global semiconductor industry. Blocked from obtaining ASML's EUV systems by US-led sanctions, China had accelerated efforts to indigenize DUV — a generation-older technology. When reports of China's potential lithography self-sufficiency surfaced, ASML's share price fell more than 8 percent in a single day. More recently, reports have emerged that Huawei is directly investing in the lithography equipment sector to speed up DUV indigenization.

As China's technological catch-up intensifies, ASML and the world's leading non-Chinese chipmakers have begun forming a united front around technology that is a step further ahead.

The immersion DUV technology China is now racing to indigenize was commercialized by ASML in the mid-to-late 2000s. Lithography technology has since evolved through EUV and on to the High-NA EUV stage. From China's perspective, it has yet to clear the hurdle of conventional EUV — yet the global leaders are already climbing the next one. That is why analysts say the non-Chinese advanced semiconductor ecosystem is erecting a new technology barrier called High-NA, even as China works to catch up with existing EUV.

China pushes DUV catch-up; non-Chinese chipmakers form united front

ASML's TWINSCAN EXE:5200B, the company's first High-NA EUV model designed for mass production. [ASML]

Here is a brief look at what each company announced alongside ASML. Intel is the furthest along. The company has already applied High-NA EUV to some products manufactured on its 18A (2-nanometer) process, with cumulative wafer starts exceeding 1 million.

Intel has also been working with ASML for more than three years on an industry initiative to transition photomasks from the current 6-inch standard to larger 12-inch formats, and is developing related standards and infrastructure together with mask manufacturers and materials suppliers.

TSMC has also moved. The company for the first time laid out concrete plans to apply High-NA EUV to advanced process mass production starting in 2030. At the same time, TSMC and ASML launched a joint industry initiative to transition the semiconductor industry's photomask standard from the current 6-inch format to a larger 12-inch format. The plan calls for establishing a 12-inch photomask pilot line by 2031, with High-NA lithography systems using those masks ready for advanced process mass production by 2033.

Samsung Electronics has joined the effort as well. The company set a target to introduce High-NA EUV into advanced DRAM manufacturing by 2028 — a first for the industry. Like Intel and TSMC, Samsung Electronics is participating in ASML's large-mask initiative, committing to develop the technology, infrastructure and standards needed to expand the photomask format from the current 6-inch to 12-inch.

Larger photomasks needed to unlock High-NA EUV efficiency; Samsung and ASML deepen ties around next-generation manufacturing standards

A photomask used in semiconductor manufacturing. [Samsung Electronics Newsroom]

Alongside the High-NA EUV equipment itself, the 12-inch large-format photomask deserves close attention.

The semiconductor industry has used 6-inch photomasks as the standard for decades. The problem is that advanced chips — AI semiconductors in particular — are growing larger and their circuit structures are becoming increasingly complex.

When an entire circuit cannot fit within a single exposure field, it must be split into multiple sections, each exposed separately and then stitched back together on the wafer. This technique is known as die stitching.

The trouble with die stitching is that any misalignment at the seams introduces defects and can require rework, inevitably lengthening process times and driving up manufacturing costs.

The semiconductor lithography process. [Samsung Electronics Newsroom]

With High-NA EUV, this burden grows even heavier. While the technology can draw far finer circuits than conventional EUV, the area it can expose in a single shot is roughly half as large. Using the existing 6-inch photomask would mean slicing circuits into even smaller pieces for each exposure.

Scaling the mask itself up to 12 inches allows more circuit information to fit on a single mask. That reduces the number of stitching operations, lowering the risk of defects and cutting manufacturing costs — while also boosting the productivity of High-NA equipment. ASML estimates that a large-format photomask system, once established, could improve High-NA system productivity by about 40 percent.

A simple analogy: rather than dividing a drawing across many small pieces and carefully reassembling them, it is far more efficient to draw the entire image on one large panel and then cut it into the sizes needed.

But this is far from a simple task. Doubling the size of the photomask alone does not solve the problem — it amounts to overhauling virtually the entire semiconductor manufacturing standard. Everything from the equipment used to make the masks, to the inspection and metrology tools that detect defects, to the systems that transport and store masks, must be redesigned from scratch to accommodate the larger format.

Fully deploying High-NA EUV in mass production while maximizing productivity ultimately requires the entire surrounding ecosystem — large-format photomasks included — to move in concert.

That is why the collaboration among ASML, Intel, TSMC and Samsung Electronics is seen as more than a simple equipment-purchasing relationship — it is a joint effort to define the next generation of semiconductor manufacturing standards. At the same time, while China works to catch up with EUV equipment itself, the non-Chinese advanced semiconductor camp is erecting yet another technology barrier: High-NA and large-format photomasks.

Samsung targets High-NA EUV for advanced DRAM in 2028; sub-10nm 0a-generation DRAM seen as likely candidate

One detail that stands out from ASML's latest round of announcements is that among the three major memory chipmakers, only Samsung Electronics issued a separate official statement jointly with ASML.

The relationship between Samsung Electronics and ASML runs deep. In March 2020, Samsung Electronics became the first memory chipmaker in the industry to apply EUV to DRAM production, supplying more than 1 million modules of first-generation 10-nanometer-class DRAM produced using EUV — validating the technology's viability for actual DRAM mass production.

The company appears to be pursuing a similar strategy with High-NA: apply the new lithography technology to actual DRAM mass production early, and use that head start to gain an edge in the race for next-generation miniaturization.

SK hynix is also preparing to adopt High-NA. The company told Reuters it is "reviewing participation in a consortium related to the introduction of 12-inch photomasks" and is targeting the application of High-NA EUV processes to DRAM mass production in 2028.

Within the industry, however, the prevailing view is that Samsung Electronics will move ahead of SK hynix on High-NA EUV adoption. One semiconductor industry official said ASML and Samsung Electronics have agreed to establish a joint R&D center in South Korea, and that Applied Materials Korea, a US semiconductor front-end equipment maker, is building a roughly 19,800-square-meter R&D collaboration center in Osan, deepening its partnership with Samsung Electronics.

Meanwhile, based on known development roadmaps, industry watchers say the likely target for High-NA EUV application is the 0a-generation DRAM — the first generation to break below the 10-nanometer threshold. Samsung Electronics is currently in the final stages of developing its seventh-generation 10-nanometer-class 1d DRAM, with early mass production expected to begin as soon as 2027. Full-scale mass production of the subsequent 0a DRAM is projected to begin around 2028.

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