SK hynix officially announced Sunday (local time) at the Hot Chips conference in Silicon Valley that its sixth-generation HBM4 12-layer product is currently in mass production and that the 16-layer product has entered the qualification stage. [Provided by SK hynix]
SK hynix officially announced Sunday (local time) at the Hot Chips conference in Silicon Valley that its sixth-generation HBM4 12-layer product is currently in mass production and that the 16-layer product has entered the qualification stage. [Provided by SK hynix]

SK hynix officially announced Sunday (local time) that its sixth-generation high bandwidth memory chip, the HBM4, is currently in mass production at the 12-layer configuration, while the 16-layer version has entered the qualification stage.

The company had previously been dogged by rumors, including speculation about supply schedule delays stemming from design changes Nvidia demanded to meet higher performance targets. Sunday's announcement reaffirmed that mass production of the 12-layer HBM4 is proceeding normally, while also providing the first concrete confirmation that the 16-layer product has advanced to the customer qualification stage.

SK hynix also outlined plans to adopt hybrid bonding — moving beyond its current MR-MUF (mass reflow molded underfill) process — to prepare for future HBM stacks of 20 or more layers.

The disclosures came during a presentation titled "Advanced Packaging for High Bandwidth Memory" delivered by Lee Jae-sik, vice president of package engineering at SK hynix America, at Hot Chips, a high-performance semiconductor and computing architecture conference held in Silicon Valley.

SK hynix's HBM4 has been the subject of persistent rumors since last year. In late 2025, reports circulated that a defect had been found in the developed product, forcing the company to redesign it from scratch. Further speculation emerged that Nvidia's decision to raise the performance target for HBM4 destined for its next-generation Rubin GPU — from 8–10 gigabits per second to 11 Gbps — was causing delays in SK hynix's HBM4 certification.

Those rumors were largely put to rest when Nvidia CEO Jensen Huang, meeting with South Korean press on June 5, said all three suppliers — Samsung Electronics, SK hynix and Micron — had passed qualification tests for HBM4.

SK hynix subsequently said during its second-quarter earnings call that HBM4 mass production supply to major customers had begun in the second quarter, with production yield and quality approaching the mature levels of its previous-generation HBM3E product, and that it was steadily ramping up supply capacity.

Lee's remarks at Hot Chips confirmed that the 16-layer HBM4 is now undergoing qualification testing. SK hynix had first unveiled a 16-layer prototype at CES 2026 earlier this year, saying at the time that development of the mass-production version was "proceeding smoothly in line with customer schedules." Sunday's comments provided a more concrete picture of where that process now stands.

Samsung Electronics, by contrast, said during its fourth-quarter 2025 earnings call in January that customer demand for a 16-layer HBM4 product was "very limited" and that, given its plans to sample a 12-layer HBM4E product of equivalent capacity this year, it saw no need to commercialize the 16-layer version in mass production. Samsung added, however, that it had already secured the technology to produce 16-layer packages at a mass-production-ready level and would have no difficulty responding if customer requirements changed.

Lee Jae-sik, vice president at SK hynix, also identified hybrid bonding as the key technology for stacking HBM beyond 16 layers to 20 or more. [Provided by SK hynix]
Lee Jae-sik, vice president at SK hynix, also identified hybrid bonding as the key technology for stacking HBM beyond 16 layers to 20 or more. [Provided by SK hynix]

Lee also identified hybrid bonding as the critical technology for stacking HBM beyond 16 layers to 20 or more. Current HBM production primarily uses a method in which microscopic bumps connect individual DRAM chips before the gaps are filled with an underfill material. As stacks grow taller, however, each DRAM chip must be made thinner, compounding the challenges of managing warpage and heat dissipation simultaneously.

Hybrid bonding takes a different approach, bonding chips directly to one another without conventional bumps. According to Lee, applying hybrid bonding allows individual DRAM dies to remain thicker within the same overall stack height while reducing the bump pitch to 18 micrometers or less, improving both performance and thermal efficiency at the same time.

SK hynix said it is focusing on two core elements to drive future HBM performance gains. "One is expanding data I/O — the number of pins, or pathways through which data flows — and increasing the speed per I/O to broaden bandwidth," Lee said. "The other is improving power efficiency through the logic die and a greater number of TSVs," referring to through-silicon via interconnects.


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