A paper on co-packaged optics technology for high-performance computing and AI, co-authored by Hong Seung-hun, an SK hynix team leader, left, and Lee Gyu-sang, a professor at the University of Virginia, has been published in the international academic journal Nature Electronics. [SK hynix]
A paper on co-packaged optics technology for high-performance computing and AI, co-authored by Hong Seung-hun, an SK hynix team leader, left, and Lee Gyu-sang, a professor at the University of Virginia, has been published in the international academic journal Nature Electronics. [SK hynix]

SK hynix has unveiled a next-generation optical technology designed to eliminate data-movement bottlenecks — one of the most persistent challenges in large-scale AI systems — and signaled plans to bring it to market.

By replacing conventional copper wiring with light to move data, the new technology is expected to solve the so-called "bandwidth wall" problem and become a key enabler of next-generation, hyperscale AI infrastructure.

SK hynix said Thursday that a paper titled "Co-Packaged Optics Technology for High-Performance Computing and AI" had been published in the international academic journal Nature Electronics.

The paper lists Hong Seung-hun, head of SK hynix's AI infrastructure team, and Lee Gyu-sang, a professor of electrical and computer engineering at the University of Virginia, as corresponding authors. Researchers from the University of Illinois Urbana-Champaign, Nanyang Technological University, the Massachusetts Institute of Technology and Yonsei University also contributed to the study.

Co-packaged optics integrates optical engines ever closer to the processor, improving bandwidth and energy efficiency as the distance electrical signals must travel is minimized. [SK hynix]
Co-packaged optics integrates optical engines ever closer to the processor, improving bandwidth and energy efficiency as the distance electrical signals must travel is minimized. [SK hynix]

Current AI systems rely on long copper wiring to transfer data between chips, but the researchers propose co-packaged optics, or CPO — a next-generation optical interconnect technology that uses light instead — as the alternative.

With copper, signal strength degrades over distance while latency and power consumption surge. Computing performance has been growing roughly threefold every two years, yet data-transfer bandwidth has increased by only about 1.4 times over the same period, making the bandwidth wall an increasingly urgent problem.

The researchers identify CPO as the key technology for breaking through that barrier. "It places an optical transceiver inside the same package as the processor, so chips can exchange data via light rather than long electrical wiring," Hong said.

The closer the optical engine sits to the processor, the shorter the distance electrical signals must travel, improving both bandwidth and energy efficiency. The technology enables fast data exchange not only between chips but also across server racks and pods, maintaining signal integrity with strong resistance to electromagnetic interference.

A conceptual diagram of an optics-centric architecture in which computing resources (XPU Pool) and memory resources (Memory Pool) are directly connected via optical signals through an optical interposer. [SK hynix]
A conceptual diagram of an optics-centric architecture in which computing resources (XPU Pool) and memory resources (Memory Pool) are directly connected via optical signals through an optical interposer. [SK hynix]

Hyperscale AI models rely on thousands of AI accelerators and HBM chips distributed across multiple servers, racks and pods working in concert. As a result, overall AI system performance is increasingly determined not by the capability of individual HBM chips but by how quickly data can move between chips, servers and racks.

The researchers set out target specifications for next-generation AI infrastructure: bandwidth exceeding 100 terabits per second, energy consumption below 1 picojoule per bit, and chip-to-chip latency under 10 nanoseconds. The paper also maps a technology roadmap progressing from conventional two-dimensional packaging to 2.5D interposers and then to three-dimensional heterogeneous integration, identifying commercialization as a central challenge.

The longer-term goal is to extend optical connectivity to the memory interface itself. While processors and memory have traditionally exchanged data via electrical signals, the plan calls for direct optical connections through an optical interposer — a step the researchers say would ease packaging space constraints and raise both the speed and efficiency of data movement.

"As customers' AI systems grow larger, the importance of optical interconnects will only increase," Hong said. "The role of memory companies is also evolving — moving beyond simply supplying products toward jointly strengthening the overall competitiveness of customers' systems."

"Extending optical connectivity to memory would reduce the physical space constraints around compute chips, overcoming limits on memory capacity and the number of interconnects," Lee said. "Multiple accelerators could share a vast memory pool, allowing AI models to scale more flexibly as they grow larger."

The paper carries added weight because SK hynix — having already driven innovation through HBM — is proactively laying out a blueprint for next-generation AI infrastructure that extends beyond a single product to encompass the entire system.

"The value of this paper lies not merely in introducing new technologies, but in systematizing a comprehensive technology roadmap for how memory, packaging and optical interconnects should converge and evolve together," SK hynix said.


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