The logo of TSMC, the world's largest semiconductor foundry. [Reuters]
The logo of TSMC, the world's largest semiconductor foundry. [Reuters]

TSMC, the world's largest semiconductor foundry, has begun developing a packaging technology similar to Intel's EMIB.

Taiwanese media outlets including United Daily News and Liberty Times reported Monday, citing sources, that TSMC has moved to prevent customers from defecting due to supply shortages of its advanced CoWoS (Chip on Wafer on Substrate) packaging technology.

Intel's EMIB (Embedded Multi-die Interconnect Bridge) is one of the leading 2.5D packaging technologies alongside TSMC's CoWoS, and has established itself as a key technology in AI semiconductors and high-performance computing.

According to the sources, TSMC has launched a project to secure an edge in advanced packaging and has begun developing an "EMIB-like" packaging technology in partnership with Taiwanese technology firm Kinsus. The sources said Kinsus is supporting TSMC's effort to advance the new packaging architecture from the research and development stage to mass production.

The sources said that if TSMC succeeds in developing the EMIB-like technology, it would cement its leading position in advanced packaging while reducing the risk of losing major customers such as Nvidia and Google to Intel.

They added that a new approach is needed to fend off Intel's challenge, as production orders for TSMC's miniaturized CoWoS-L are fully booked through 2027, pushing lead times — the time from order placement to product delivery — to as long as 78 weeks.

A separate source said Intel's EMIB-T yield rate is approaching 90 percent and its cost is about 50 percent lower than TSMC's CoWoS, with the only drawback being that substrate yields remain at around 50 percent.

TSMC's CoWoS is an advanced packaging process that stacks GPU and HBM chips on a single substrate to boost processing performance while saving space and reducing power consumption.

Intel's EMIB, by contrast, embeds silicon bridges directly into the packaging substrate rather than using an RDL (Redistribution Layer) — the metal wiring and insulating layers formed on top of chips to create electrical connections — cutting costs and saving space by reducing process complexity.

Earlier, at its second-quarter earnings call in mid-July, TSMC said demand for AI chips on advanced process nodes is very strong, that demand from major customers and cloud service providers continues to grow, and that order visibility already extends through 2029 to 2030.

TSMC also raised its annual capital expenditure outlook — a key indicator of management's confidence in the sustainability of AI demand — from around $50 billion to between $60 billion and $64 billion.


yckim6452@heraldcorp.com